As semiconductor devices continue to get smaller and technology nodes shrink into the lower nanometer range, device scaling needs to continue to provide both lower cost and improved performance. Tip to tip patterning of lines with minimum spacing is critical and extremely challenging. Electrical shorts and opens result with existing via patterning processes. Patterning is even more of a challenge when the via (e.g., self-aligned via (SAV)) is formed at the end of the lines.
A need therefore exists for methodology enabling the formation of line end vias without the risk of electrical shorts, and the resulting device.